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NTSYSpc is scheduled for the following release date:1. Field of the Invention
The present invention relates to a memory tester for testing a memory, and more particularly, to a memory tester for testing a memory, in which a memory cell test is preferably executed.
2. Description of the Related Art
A memory tester may detect a deterioration failure of a memory cell by performing a read-modify-write operation at high speed.
When a nonvolatile memory (NVRAM) is read-modify-written, the data is written to the memory cell and then the data is read from the memory cell.
FIG. 1 is a block diagram illustrating a conventional memory tester, and FIG. 2 is a flowchart illustrating the conventional memory tester. The conventional memory tester comprises a controller 10, an input/output (I/O) unit 20, a main controller 30, and a core unit 40.
Referring to FIG. 1, the controller 10 is connected to an input unit 11 for receiving a command and data required for a write operation and a read operation. The input unit 11 is connected to the I/O unit 20 for receiving the command and data required for the write operation and the read operation from a host device (not shown).
The I/O unit 20 is connected to the core unit 40 for outputting the command and data required for the write operation and the read operation to the host device. The I/O unit 20 is also connected to a memory tester board 50 for receiving the command and data required for the write operation and the read operation, and outputting the command and data to the memory cell to be tested. The I/O unit 20 is further connected to a core unit buffer 60 for storing the command and data required for the write operation and the read operation.
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